Sparcle: an evolutionary processor design for large-scale multiprocessors
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Micro
M. Parkin
G. D’Souza
D. Yeung
B.H. Lim
D. Kranz
D.T. Blaauw
Anatomy of a message in the Alewife multiprocessor
Routing architecture exploration for regular fabrics