A pattern based instruction encoding technique for high performance architectures
2D-VLIW: An Architecture Based on the Geometry of Computation
A New Technique for Instruction Encoding in High Performance Architectures
The 2D-VLIW Architecture
IC Technical Reports 2006
IJHPSA
IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP’06)
IC Technical Reports 2007
Rodolfo Jardim de Azevedo
Guido Araújo
Rafael Fernandes Batistella