Register Pointer Architecture for Efficient Embedded Processors
Route packets, net wires
21st century digital design tools
Efficient Embedded Computing
Explaining the gap between ASIC and custom power
Interconnect routing and scheduling—Adaptive routing in high-radix clos network
Proceedings of the 2006 ACM/IEEE conference on Supercomputing - SC ’06
Proceedings of the 34th annual international symposium on Computer architecture - ISCA ’07
Proceedings of the 50th Annual Design Automation Conference on - DAC ’13
Proceedings of the 20th annual international symposium on Computer architecture - ISCA ’93
Computer
Proceedings of the 38th conference on Design automation - DAC ’01
JongSoo Park
Dennis Abts
John Kim
Chris Malachowsky
David Black-Schaffer
James D. Balfour
HyperX: Topology, Routing, and Packaging of Efficient Large-scale Networks
A lightweight idempotent messaging protocol for faulty networks
Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs Affordable